CA1289664C - Pulse width decoder for double frequency encoded serial data - Google Patents

Pulse width decoder for double frequency encoded serial data

Info

Publication number
CA1289664C
CA1289664C CA000466651A CA466651A CA1289664C CA 1289664 C CA1289664 C CA 1289664C CA 000466651 A CA000466651 A CA 000466651A CA 466651 A CA466651 A CA 466651A CA 1289664 C CA1289664 C CA 1289664C
Authority
CA
Canada
Prior art keywords
waveform
logical
responsive
inputted
flipflop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CA000466651A
Other languages
English (en)
French (fr)
Inventor
Bernardo A/K/A Levy Bernardo Levy-Navarro
Ensi Parkar Sylvernale
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Unisys Corp
Original Assignee
Unisys Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Unisys Corp filed Critical Unisys Corp
Application granted granted Critical
Publication of CA1289664C publication Critical patent/CA1289664C/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1407—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol
    • G11B20/1419—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol to or from biphase level coding, i.e. to or from codes where a one is coded as a transition from a high to a low level during the middle of a bit cell and a zero is encoded as a transition from a low to a high level during the middle of a bit cell or vice versa, e.g. split phase code, Manchester code conversion to or from biphase space or mark coding, i.e. to or from codes where there is a transition at the beginning of every bit cell and a one has no second transition and a zero has a second transition one half of a bit period later or vice versa, e.g. double frequency code, FM code

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
CA000466651A 1983-10-31 1984-10-30 Pulse width decoder for double frequency encoded serial data Expired - Lifetime CA1289664C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/547,382 US4547764A (en) 1983-10-31 1983-10-31 Pulse width decoder for double frequency encoded serial data
US547,382 1983-10-31

Publications (1)

Publication Number Publication Date
CA1289664C true CA1289664C (en) 1991-09-24

Family

ID=24184439

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000466651A Expired - Lifetime CA1289664C (en) 1983-10-31 1984-10-30 Pulse width decoder for double frequency encoded serial data

Country Status (6)

Country Link
US (1) US4547764A (en])
EP (1) EP0140703B1 (en])
JP (1) JPS61500294A (en])
CA (1) CA1289664C (en])
DE (1) DE3481956D1 (en])
WO (1) WO1985002074A1 (en])

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4763338A (en) * 1987-08-20 1988-08-09 Unisys Corporation Synchronous signal decoder
US5140611A (en) * 1989-09-29 1992-08-18 Rockwell International Corporation Pulse width modulated self-clocking and self-synchronizing data transmission and method for a telephonic communication network switching system
US5168275A (en) * 1990-02-07 1992-12-01 International Business Machines Corporation Method and apparatus for decoding two frequency (f/2f) data signals
SE466725B (sv) * 1990-07-18 1992-03-23 Goeran Krook Foerfarande foer att begraensa bandbredden hos en godtycklig binaer signal
US5696800A (en) * 1995-03-22 1997-12-09 Intel Corporation Dual tracking differential manchester decoder and clock recovery circuit
EP0778517A3 (en) * 1995-11-27 1998-02-11 Texas Instruments Incorporated Improvements in or relating to the encoding of an image control signal
US7760835B2 (en) * 2002-10-02 2010-07-20 Battelle Memorial Institute Wireless communications devices, methods of processing a wireless communication signal, wireless communication synchronization methods and a radio frequency identification device communication method

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3237176A (en) * 1962-01-26 1966-02-22 Rca Corp Binary recording system
US3448445A (en) * 1965-06-17 1969-06-03 Rca Corp Conversion from self-clocking code to nrz code
US3737632A (en) * 1972-03-23 1973-06-05 R Barnes Rate adaptive nonsynchronous demodulator apparatus for biphase binary signals
US4027267A (en) * 1976-06-01 1977-05-31 International Business Machines Corporation Method of decoding data content of F2F and phase shift encoded data streams
US4344039A (en) * 1979-03-13 1982-08-10 Sanyo Electric Co., Ltd. Demodulating circuit for self-clocking-information
US4320525A (en) * 1979-10-29 1982-03-16 Burroughs Corporation Self synchronizing clock derivation circuit for double frequency encoded digital data

Also Published As

Publication number Publication date
US4547764A (en) 1985-10-15
EP0140703A3 (en) 1987-09-02
EP0140703B1 (en) 1990-04-11
EP0140703A2 (en) 1985-05-08
DE3481956D1 (de) 1990-05-17
JPH0213494B2 (en]) 1990-04-04
JPS61500294A (ja) 1986-02-20
WO1985002074A1 (en) 1985-05-09

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